8 bit GCD PROCESSOR

//Main Module for GCD

module gcd(a,b,clk,rst,subout);

input [7:0]a,b;

input clk,rst;

output [7:0]subout;

wire [7:0]regx,regy;

wire [1:0]s;

wire g,z;

wire [2:0]d;

cont c1(g,z,clk,rst,s,d);

mux m1(a,b,regx,regy,subout,s,d,clk,rst);

func f1(regx,regy,d,clk,rst,g,z);

endmodule

//Main Module for MUX

module mux(a,b,regx,regy,subout,s,d,clk,rst);

input [7:0]a,b;

input clk,rst;

input [1:0]s;

input [2:0]d;

output reg [7:0]regx,regy,subout;

reg [7:0]sw;

always@(posedge clk)

begin

if(rst)

begin

regx=a;

regy=b;

subout=8'b0;

end

else

begin

if(d==3'b100)

begin

case(s)

0:begin

regx=regx;

regy=regy;

end

1:begin

regx=regx-regy;

end

2:begin

sw=regx;

regx=regy;

regy=sw;

end

3:begin

subout=regy;

regx=8'b0;

regy=regy;

end

endcase

end

end

end

endmodule

//Sub Module for count

module cont(x,y,clk,rst,s,d);

input x,y,clk,rst;

output [1:0]s;

output reg[2:0]d;

reg [1:0]s;

always@(posedge clk)

begin

if(rst)

begin

s=2'b00;

d=3'b001;

end

else if(!rst)

begin

if(d==3'b001)

begin

d={d[0],d[2:1]};

if({x,y}==2'b11)

s=2'b00;

else if({x,y}==2'b10)

s=2'b01;

else if({x,y}==2'b00)

s=2'b10;

else if({x,y}==2'b01)

s=2'b11;

end

else

d={d[0],d[2:1]};

end

end

endmodule

//Sub Module for function

module func(rex,regy,de,clk1,rst1,g,z);

input [7:0]rex,regy;

input clk1,rst1;

input [2:0]de;

output reg g,z;

always@(posedge clk1)

begin

if(!rst1)

begin

if(de==3'b010)

begin

if(rex>=regy)

g=1;

else

g=0;

if(rex==0)

z=1;

else

z=0;

end

end

else

begin

if(rst1)

begin

g=1;

z=1;

end

end

end

endmodule