8 bit ALU UNIT

//main module for alu

module alu(a,b,op,decode,clk,out);

input [7:0]a,b;

input [5:0]decode;

input clk;

input[3:0]op;

output [7:0]out;

reg [7:0]out;

wire [7:0]quo;

div8 s1(a,b,quo);

always@(posedge clk)

begin

if(decode==6'b000100)

begin

case(op)

0 : out=a;

1 : out=a+b;

2 : out=a-b;

3 : out=a*b;

4 : out=quo;

5 : out=a&b;

6: out=a|b;

7 : out=a^b;

8 : out=b<<1;

9 : out=b>>1;

10 : out={b[0],b[7:1]};

11 : out={b[6:0],b[7]};

endcase

end

end

endmodule

//submodule

module div8(divs,divd,quo);

input [7:0]divs;

input [7:0]divd;

output [7:0]quo;

wire [3:0]r1,r2,r3,r4,r5;

assign quo[7:5]=0;

div4 d1(divs[7:4],divd[3:0],r1[3:0],quo[4]);

div4 d2({r1[2:0],divs[3]},divd[3:0],r2[3:0],

quo[3]);

div4 d3({r2[2:0],divs[2]},divd[3:0],r3[3:0],

quo[2]);

div4 d4({r3[2:0],divs[1]},divd[3:0],r4[3:0],

quo[1]);

div4 d5({r4[2:0],divs[0]},divd[3:0],r5[3:0],

quo[0]);

endmodule

//sub module

module div4(divs,divd,rem,quo);

input [3:0]divs,divd;

output [3:0]rem;

output quo;

reg [3:0]rem;

reg quo;

wire [3:0]r,c;

cas1 c1(divs[0],divd[0],1'b0,r[0],c[0]);

cas1 c2(divs[1],divd[1],c[0],r[1],c[1]);

cas1 c3(divs[2],divd[2],c[1],r[2],c[2]);

cas1 c4(divs[3],divd[3],c[2],r[3],c[3]);

always@(divs or c or r)

begin

if(c[3])

begin

quo=1'b0;

rem=divs;

end

else

begin

quo=1'b1;

rem=r;

end

end

endmodule

//sub module

module cas1(a,b,c,diff,brow);

input a,b,c;

output diff,brow;

assign diff=a^b^c;

assign brow=((~a)&b)|(b&c)|((~a)&c);

endmodule