module
rip(s,cout,a,b,cin);
//main
module of 16 bit Ripple carry adder
input
[15:0]a;
input
[15:0]b;
input
cin;
output
cout;
output
[15:0]s;
wire
c4,c8,c12,cout;
rip2
m1(s[3:0],c4,a[3:0],b[3:0],cin);
rip2
m2(s[7:4],c8,a[7:4],b[7:4],c4);
rip2
m3(s[11:8],c12,a[11:8],b[11:8],c8);
rip2
m4(s[15:12],cout,a[15:12],b[15:12],c12);
endmodule
module
rip2(s,cout,a,b,cin);
//sub module for 4 bit Ripple carry adder
input [3:0]a;
input [3:0]b;
input cin;
output cout;
output [3:0]s;
wire c2,c3,c4,cout;
fa m1(s[0],c2,a[0],b[0],cin);
fa m2(s[1],c3,a[1],b[1],c2);
fa m3(s[2],c4,a[2],b[2],c3);
fa m4(s[3],cout,a[3],b[3],c4);
endmodule
module
fa(s,cout,a,b,cin);
//sub
module for Full adder
input
a,b,cin;
output
s,cout;
wire
w1,w2,w3;
ha
m1(w1,w2,a,b);
ha
m2(s,w3,w1,cin);
or
m3(cout,w2,w3);
endmodule
module
ha(s,cout,a,b);
//sub module for Half adder
input a,b;
output s,cout;
xor m1(s,a,b);
and m2(cout,a,b);
endmodule
hi there can i have verilog for "ripple-carry adder and 4-bit block carry skip adder"...
ReplyDeleteAnyone please send me the 'behavioral model' and 'test bench model' of a BIST state machine which can perform on 16-byte register.
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