//Main
module for Multirate Processing
module
multi(in,q,out,clk);
input
[7:0]in;
input
q;
output
clk;
output
[15:0]out;
wire
clk;
wire
[15:0]out1,out2,out3;
wire
clk1,clk2;
bpsk
q1(in,clk,out1);
qpsk
q2(in,clk1,out2);
qamp
q3(in,clk2,out3);
dff
q4(clk,clk1);
dff
q6(clk1,clk2);
div
q5(q,rst,clk);
assign
out=out3;
endmodule
//Sub
Module for BPSK
module
bpsk(in,clk,out);
input
[7:0]in;
input
clk;
output
[15:0]out;
reg
[7:0]ar,ai;
reg
[2:0]cn;
reg
[7:0]pr;
reg
s;
parameter
ap=8'b10110100;//positive .707
parameter
an=8'b01001100;//negative -.707
represent
in 2's complement
initial
begin
cn=3'b000;
pr=in;
end
always@(posedge
clk)
begin
case(cn)
0
: begin
s=in[0];
cn=3'b001;
end
1
: begin
s=in[1];
cn=3'b010;
end
2
: begin
s=in[2];
cn=3'b011;
end
3
: begin
s=in[3];
cn=3'b100;
end
4
: begin
s=in[4];
cn=3'b101;
end
5
: begin
s=in[5];
cn=3'b110;
end
6
: begin
s=in[6];
cn=3'b111;
end
7
: begin
s=in[7];
if(pr!=in)
begin
cn=3'b000;
pr=in;
end
end
endcase
case(s)
0
: begin
ar=ap;
ai=ap;
end
1
: begin
ar=an;
ai=ap;
end
endcase
end
assign
out={ar,ai};
endmodule
//Sub
module for QPSK
module
qpsk(in,clk,out);
input
[7:0]in;
input
clk;
output
[15:0]out;
reg [7:0]ar,ai;
reg
[1:0]cn,s;
reg
[7:0]pr;
parameter
ap=8'b10110100;//positive .707
parameter
an=8'b01001100;//negative -.707
represent
in 2's complement
initial
begin
cn=2'b0;
pr=in;
end
always@(posedge
clk)
begin
case(cn)
0
: begin
s=in[1:0];
cn=2'b01;
end
1
: begin
s=in[3:2];
cn=2'b10;
end
2
: begin
s=in[5:4];
cn=2'b11;
end
3
: begin
s=in[7:6];
if(pr!=in)
begin
cn=2'b0;
pr=in;
end
end
endcase
case(s)
0
: begin
ar=ap;
ai=ap;
end
1
: begin
ar=ap;
ai=an;
end
2
: begin
ar=an;
ai=ap;
end
3
: begin
ar=an;
ai=an;
end
endcase
end
assign
out={ar,ai};
endmodule
//Sub
module for 16-QAM
module
qamp(in,clk,out);
parameter
ap=8’b01010000;
parameter
an=8’b10110000;
parameter
bp=8’b11110010;
parameter
bn=8’b00001110;
input
[7:0]in;
input
clk;
output
[15:0]out;
reg
[7:0]i,q,pr;
reg
[3:0]s;
reg
cn;
initial
begin
cn=0;
pr=in;
end
always@(posedge
clk)
begin
case(cn)
0
: begin
s=in[3:0];
cn=1;
end
1
: begin
s=in[7:4];
if(pr!=in)
begin
cn=0;
pr=in;
end
end
endcase
case(s)
0
: begin
i=ap;
q=ap;
end
1
: begin
i=ap;
q=bp;
end
2
: begin
i=bp;
q=ap;
end
3
: begin
i=bp;
q=bp;
end
4
: begin
i=ap;
q=an;
end
5
: begin
i=ap;
q=bn;
end
6:
begin
i=bp;
q=an;
end
7
: begin
i=bp;
q=bn;
end
8
: begin
i=an;
q=ap;
end
9
: begin
i=an;
q=bp;
end
10
: begin
i=bn;
q=ap;
end
11
: begin
i=bn;
q=bp;
end
12
: begin
i=an;
q=an;
end
13
: begin
i=an;
q=bn;
end
14
: begin
i=bn;
q=an;
end
15
: begin
i=bn;
q=bn;
end
endcase
end
assign
out={i,q};
endmodule
//Sub
module Clock Divider
module
div(clk,rst,q);
input
clk,rst;
output
q;
reg
[27:0]sig;
always
@(posedge clk)
begin
if(rst==1)
sig=28'b0;
else
if (rst==0)
sig=sig+1;
end
assign
q=sig[25];
endmodule
module
dff(clk,clk1);
input
clk;
output
reg clk1;
initial
begin
clk1=1'b0;
end
always@(posedge
clk)
begin
clk1=~clk1;
end
endmodule
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