Asynchronous Bus Transmitter and receiver

Transmitter

module trans(clk, TxD_start, TxD_data, bus,asynout, TxD_busy,BaudTick);

input clk, TxD_start;

input [7:0] TxD_data;

output bus,asynout,TxD_busy,BaudTick;

wire q;

div Baudgenerate(clk,q);

reg [3:0] state;

wire TxD_ready, TxD_busy;

reg [7:0] TxD_dataD;

reg muxbit;

reg [3:0] count;

wire BaudTick = count[3];

always @(posedge q) if(TxD_busy) count <= count[2:0]+1;

assign TxD_ready = (state==0);

assign TxD_busy = ~TxD_ready;

always @(posedge q)  if (TxD_ready & TxD_start) TxD_dataD = TxD_data;

always @(posedge q)

case(state)

                4'b0000: if(TxD_start) state <= 4'b0001;

                4'b0001: if(BaudTick) state <= 4'b0100;

                4'b0100: if(BaudTick) state <= 4'b1000;  // start

                4'b1000: if(BaudTick) state <= 4'b1001;  // bit 0

                4'b1001: if(BaudTick) state <= 4'b1010;  // bit 1

                4'b1010: if(BaudTick) state <= 4'b1011;  // bit 2

                4'b1011: if(BaudTick) state <= 4'b1100;  // bit 3

                4'b1100: if(BaudTick) state <= 4'b1101;  // bit 4

                4'b1101: if(BaudTick) state <= 4'b1110;  // bit 5

                4'b1110: if(BaudTick) state <= 4'b1111;  // bit 6

                4'b1111: if(BaudTick) state <= 4'b0010;  // bit 7

                4'b0010: if(BaudTick) state <= 4'b0011; // stop1

                4'b0011: if(BaudTick) state <= 4'b0000;  // stop2

                default: if(BaudTick) state <= 4'b0000;

endcase

always @(state[2:0])

case(state[2:0])

                3'd0: muxbit <= TxD_dataD[0];

                3'd1: muxbit <= TxD_dataD[1];

                3'd2: muxbit <= TxD_dataD[2];

                3'd3: muxbit <= TxD_dataD[3];

                3'd4: muxbit <= TxD_dataD[4];

                3'd5: muxbit <= TxD_dataD[5];

                3'd6: muxbit <= TxD_dataD[6];

                3'd7: muxbit <= TxD_dataD[7];

endcase

// Put together the start, data and stop bits

reg bus,asynout;

always @(posedge q)

begin

 bus <= (state<4) | (state[3] & muxbit);

asynout= (~(state[3]) && ~(state[2]) && ~(state[1]) && (state[0]));

end

endmodule

module div(clk,q);

input clk;

output q;

reg [27:0]sig;

always @(posedge clk)

begin

sig=sig+1;

end

assign q=sig[24];

endmodule

Receiver

module receive(clk, bus,asynin, RxD_data,RxD_ready,BaudTick);

input clk, bus,asynin;

output [7:0] RxD_data;

output RxD_ready,BaudTick;

wire q;

div Baudgenerate(clk,q);

reg [3:0] state;

wire RxD_ready,x;

wire bus;

reg st;

reg [3:0] baudcount;

wire BaudTick = baudcount[3];

always @(posedge q) if(state!=0) baudcount <= baudcount[2:0]+1;

initial begin state=0; st=0; baudcount=0; end

//identify start bit

always @(posedge q)

case(st)

 0: if(bus==0 && asynin==0 ) st=1; //when bus is idle, check for start identified

 1: if (state==4'b0011) st=0;//receive state

endcase

assign x= (st==0);

assign RxD_ready = ~x;

reg RxD_bit;

always @(posedge q)  if (asynin==0) RxD_bit = bus;

always @(posedge q)

case(state)

  4'b0000: if(RxD_ready) state <= 4'b0001;  // idle

  4'b0001: if(BaudTick) state <= 4'b1000;  // start bit

  4'b1000: if(BaudTick) state <= 4'b1001;  // bit 1

  4'b1001: if(BaudTick) state <= 4'b1010;  // bit 2

  4'b1010: if(BaudTick) state <= 4'b1011;  // bit 3

  4'b1011: if(BaudTick) state <= 4'b1100;  // bit 4

  4'b1100: if(BaudTick) state <= 4'b1101;  // bit 5

  4'b1101: if(BaudTick) state <= 4'b1110;  // bit 6

  4'b1110: if(BaudTick) state <= 4'b1111;  // bit 7

  4'b1111: if(BaudTick) state <= 4'b0010;  // bit 8

    4'b0010: if(BaudTick) state <= 4'b0011;  // stop1

  4'b0011: state <= 4'b0000;  // stop2

                default: state <= 4'b0000;

endcase

reg [7:0] RxD_data;

always @(posedge q)

if(BaudTick && state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};

endmodule

module div(clk,q); // Sub module for clock division

input clk;

output q;

reg [27:0]sig;

always @(posedge clk)

begin

sig=sig+1;

end

assign q=sig[24];

endmodule