8 POINT DCT

module dct1(sel,y);

  input [2:0]sel;

  output reg [15:0]y; 

  wire [15:0]y0,y1,y2,y3,y4,y5,y6,y7;

  wire [7:0]p0,p1,p2,p3,p10,p11,p100,m0,m1,m2,m3,m10,m11,m100;

  wire [15:0]n0,n1,n2,n3,q0,q1,q2,q3;

  wire [7:0]x0,x1,x2,x3,x4,x5,x6,x7;

parameter c1=8'b11111011;

parameter c2=8'b11101100;

parameter c3=8'b11010100;

parameter c4=8'b10110101;

parameter c5=8'b10001110;

parameter c6=8'b01100001;

parameter c7=8'b00110001;

assign x0=8'b10110;

assign x1=8'b1001;

assign x2=8'b101;

assign x3=8'b1111;

assign x4=8'b1011;

assign x5=8'b10;

assign x6=8'b100;

assign x7=8'b10010;

//stage1

bfly1 s11(x0,x7,p0,m0);

bfly1 s12(x3,x4,p1,m1);

bfly1 s13(x1,x6,p2,m2); 

bfly1 s14(x2,x5,p3,m3);

//stage2

bfly2 s21(m0,m1,c1,c7,n0,q0); 

bfly2 s22(m2,m3,c3,c5,n1,q1);

bfly2 s23(m0,m1,c5,c3,n2,q2);

bfly2 s24(m2,m3,c7,c1,n3,q3);

bfly1 s15(p0,p1,p10,m10);

bfly1 s16(p2,p3,p11,m11);

//stage3

bfly2 s31(m10,m11,c2,c6,y2,y6);

bfly1 s32(p10,p11,p100,m100);

assign y1=n0+n1;

assign y7=q0+(~q1+1);

assign y5=n2+(~q3+1);

assign y3=q2+(~n3+1);

assign y0=p100*c4;

assign y4=m100*c4;

always@(sel)

case(sel)

  0:begin y=y0; end

  1:begin y=y1; end

  2:begin y=y2; end

  3:begin y=y3; end

  4:begin y=y4; end

  5:begin y=y5; end

  6:begin y=y6; end

  7:begin y=y7; end

endcase

 endmodule

module bfly1(x,y,p,m);

  input [7:0]x,y;

  output[7:0]p,m;

  assign p=x+y;

  assign m=x+(~y+1);

  endmodule

module bfly2(x,y,cx,cy,sx,sy);

  input [7:0]x,y,cx,cy;

  output [15:0]sx,sy;

   assign sx=(x*cx)+(y*cy);

  assign sy=(x*cy)+(~(y*cx)+1);

endmodule

MULTIRATE PROCESSING TECHNIQUE(BPSK,QPSK,QAM)

 //Main module for Multirate Processing

module multi(in,q,out,clk);

input [7:0]in;

input q;

output clk;

output [15:0]out;

wire clk;

wire [15:0]out1,out2,out3;

wire clk1,clk2;

bpsk q1(in,clk,out1);

qpsk q2(in,clk1,out2);

qamp q3(in,clk2,out3);

dff q4(clk,clk1);

dff q6(clk1,clk2);

div q5(q,rst,clk);

assign out=out3;

endmodule

//Sub Module for BPSK

module bpsk(in,clk,out);

input [7:0]in;

input clk;

output [15:0]out;

reg [7:0]ar,ai;

reg [2:0]cn;

reg [7:0]pr;

reg s;

parameter ap=8'b10110100;//positive .707

parameter an=8'b01001100;//negative -.707

represent in 2's complement

initial

begin

cn=3'b000;

pr=in;

end

always@(posedge clk)

begin

case(cn)

0 : begin

s=in[0];

cn=3'b001;

end

1 : begin

s=in[1];

cn=3'b010;

end

2 : begin

s=in[2];

cn=3'b011;

end

3 : begin

s=in[3];

cn=3'b100;

end

4 : begin

s=in[4];

cn=3'b101;

end

5 : begin

s=in[5];

cn=3'b110;

end

6 : begin

s=in[6];

cn=3'b111;

end

7 : begin

s=in[7];

if(pr!=in)

begin

cn=3'b000;

pr=in;

end

end

endcase

case(s)

0 : begin

ar=ap;

ai=ap;

end

1 : begin

ar=an;

ai=ap;

end

endcase

end

assign out={ar,ai};

endmodule

//Sub module for QPSK

module qpsk(in,clk,out);

input [7:0]in;

input clk;

output [15:0]out;

reg  [7:0]ar,ai;

reg [1:0]cn,s;

reg [7:0]pr;

parameter ap=8'b10110100;//positive .707

parameter an=8'b01001100;//negative -.707

represent in 2's complement

initial

begin

cn=2'b0;

pr=in;

end

always@(posedge clk)

begin

case(cn)

0 : begin

s=in[1:0];

cn=2'b01;

end

1 : begin

s=in[3:2];

cn=2'b10;

end

2 : begin

s=in[5:4];

cn=2'b11;

end

3 : begin

s=in[7:6];

if(pr!=in)

begin

cn=2'b0;

pr=in;

end

end

endcase

case(s)

0 : begin

ar=ap;

ai=ap;

end

1 : begin

ar=ap;

ai=an;

end

2 : begin

ar=an;

ai=ap;

end

3 : begin

ar=an;

ai=an;

end

endcase

end

assign out={ar,ai};

endmodule

//Sub module for 16-QAM

module qamp(in,clk,out);

parameter ap=8’b01010000;

parameter an=8’b10110000;

parameter bp=8’b11110010;

parameter bn=8’b00001110;

input [7:0]in;

input clk;

output [15:0]out;

reg [7:0]i,q,pr;

reg [3:0]s;

reg cn;

initial

begin

cn=0;

pr=in;

end

always@(posedge clk)

begin

case(cn)

0 : begin

s=in[3:0];

cn=1;

end

1 : begin

s=in[7:4];

if(pr!=in)

begin

cn=0;

pr=in;

end

end

endcase

case(s)

0 : begin

i=ap;

q=ap;

end

1 : begin

i=ap;

q=bp;

end

2 : begin

i=bp;

q=ap;

end

3 : begin

i=bp;

q=bp;

end

4 : begin

i=ap;

q=an;

end

5 : begin

i=ap;

q=bn;

end

6: begin

i=bp;

q=an;

end

7 : begin

i=bp;

q=bn;

end

8 : begin

i=an;

q=ap;

end

9 : begin

i=an;

q=bp;

end

10 : begin

i=bn;

q=ap;

end

11 : begin

i=bn;

q=bp;

end

12 : begin

i=an;

q=an;

end

13 : begin

i=an;

q=bn;

end

14 : begin

i=bn;

q=an;

end

15 : begin

i=bn;

q=bn;

end

endcase

end

assign out={i,q};

endmodule

//Sub module Clock Divider

module div(clk,rst,q);

input clk,rst;

output q;

reg [27:0]sig;

always @(posedge clk)

begin

if(rst==1)

sig=28'b0;

else if (rst==0)

sig=sig+1;

end

assign q=sig[25];

endmodule

module dff(clk,clk1);

input clk;

output reg clk1;

initial

begin

clk1=1'b0;

end

always@(posedge clk)

begin

clk1=~clk1;

end

endmodule

Asynchronous Bus Transmitter and receiver

Transmitter

module trans(clk, TxD_start, TxD_data, bus,asynout, TxD_busy,BaudTick);

input clk, TxD_start;

input [7:0] TxD_data;

output bus,asynout,TxD_busy,BaudTick;

wire q;

div Baudgenerate(clk,q);

reg [3:0] state;

wire TxD_ready, TxD_busy;

reg [7:0] TxD_dataD;

reg muxbit;

reg [3:0] count;

wire BaudTick = count[3];

always @(posedge q) if(TxD_busy) count <= count[2:0]+1;

assign TxD_ready = (state==0);

assign TxD_busy = ~TxD_ready;

always @(posedge q)  if (TxD_ready & TxD_start) TxD_dataD = TxD_data;

always @(posedge q)

case(state)

                4'b0000: if(TxD_start) state <= 4'b0001;

                4'b0001: if(BaudTick) state <= 4'b0100;

                4'b0100: if(BaudTick) state <= 4'b1000;  // start

                4'b1000: if(BaudTick) state <= 4'b1001;  // bit 0

                4'b1001: if(BaudTick) state <= 4'b1010;  // bit 1

                4'b1010: if(BaudTick) state <= 4'b1011;  // bit 2

                4'b1011: if(BaudTick) state <= 4'b1100;  // bit 3

                4'b1100: if(BaudTick) state <= 4'b1101;  // bit 4

                4'b1101: if(BaudTick) state <= 4'b1110;  // bit 5

                4'b1110: if(BaudTick) state <= 4'b1111;  // bit 6

                4'b1111: if(BaudTick) state <= 4'b0010;  // bit 7

                4'b0010: if(BaudTick) state <= 4'b0011; // stop1

                4'b0011: if(BaudTick) state <= 4'b0000;  // stop2

                default: if(BaudTick) state <= 4'b0000;

endcase

always @(state[2:0])

case(state[2:0])

                3'd0: muxbit <= TxD_dataD[0];

                3'd1: muxbit <= TxD_dataD[1];

                3'd2: muxbit <= TxD_dataD[2];

                3'd3: muxbit <= TxD_dataD[3];

                3'd4: muxbit <= TxD_dataD[4];

                3'd5: muxbit <= TxD_dataD[5];

                3'd6: muxbit <= TxD_dataD[6];

                3'd7: muxbit <= TxD_dataD[7];

endcase

// Put together the start, data and stop bits

reg bus,asynout;

always @(posedge q)

begin

 bus <= (state<4) | (state[3] & muxbit);

asynout= (~(state[3]) && ~(state[2]) && ~(state[1]) && (state[0]));

end

endmodule

module div(clk,q);

input clk;

output q;

reg [27:0]sig;

always @(posedge clk)

begin

sig=sig+1;

end

assign q=sig[24];

endmodule

Receiver

module receive(clk, bus,asynin, RxD_data,RxD_ready,BaudTick);

input clk, bus,asynin;

output [7:0] RxD_data;

output RxD_ready,BaudTick;

wire q;

div Baudgenerate(clk,q);

reg [3:0] state;

wire RxD_ready,x;

wire bus;

reg st;

reg [3:0] baudcount;

wire BaudTick = baudcount[3];

always @(posedge q) if(state!=0) baudcount <= baudcount[2:0]+1;

initial begin state=0; st=0; baudcount=0; end

//identify start bit

always @(posedge q)

case(st)

 0: if(bus==0 && asynin==0 ) st=1; //when bus is idle, check for start identified

 1: if (state==4'b0011) st=0;//receive state

endcase

assign x= (st==0);

assign RxD_ready = ~x;

reg RxD_bit;

always @(posedge q)  if (asynin==0) RxD_bit = bus;

always @(posedge q)

case(state)

  4'b0000: if(RxD_ready) state <= 4'b0001;  // idle

  4'b0001: if(BaudTick) state <= 4'b1000;  // start bit

  4'b1000: if(BaudTick) state <= 4'b1001;  // bit 1

  4'b1001: if(BaudTick) state <= 4'b1010;  // bit 2

  4'b1010: if(BaudTick) state <= 4'b1011;  // bit 3

  4'b1011: if(BaudTick) state <= 4'b1100;  // bit 4

  4'b1100: if(BaudTick) state <= 4'b1101;  // bit 5

  4'b1101: if(BaudTick) state <= 4'b1110;  // bit 6

  4'b1110: if(BaudTick) state <= 4'b1111;  // bit 7

  4'b1111: if(BaudTick) state <= 4'b0010;  // bit 8

    4'b0010: if(BaudTick) state <= 4'b0011;  // stop1

  4'b0011: state <= 4'b0000;  // stop2

                default: state <= 4'b0000;

endcase

reg [7:0] RxD_data;

always @(posedge q)

if(BaudTick && state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};

endmodule

module div(clk,q); // Sub module for clock division

input clk;

output q;

reg [27:0]sig;

always @(posedge clk)

begin

sig=sig+1;

end

assign q=sig[24];

endmodule