IIR FILTER

//mainmodule for iir unit
module iir(clk,rst,out);
  input clk,rst;
  output [7:0]out;
  parameter p0=8'b00100000;
  parameter p1=8'b00010000;
  parameter p2=8'b00001000;
  parameter p3=8'b00000100;
  parameter d3=8'b00100100;
  parameter d2=8'b00011000;
  parameter d1=8'b00001100;
  wire [7:0]y1,y2,y3,y4,y5,y6,f1,f2,f3,f4,f5,x5,x1,x2,x3,x4,w,x6,x,a1,a2,a3;
  wire q;
  div cld(clk,rst,q);
  count c(q,rst,x);
  div82 s1(x,p0,y1);
  div82 s2(x,p1,y2);
  div82 s3(x,p2,y3);
  div82 s4(x,p3,y4);
  register s5(y4,q,rst,x1);
  assign y5=x1+y3;
  register s6(y5,q,rst,x2);
  assign y6=x2+y2;
  register s7(y6,q,rst,x3);
  assign w=x3+y1;
  div82 s8(out,d3,f1);
  div82 s9(out,d2,f2);
  div82 s10(out,d1,f3);
  register s11(f1,q,rst,x4);
  assign a1=~f2+1;
  assign f4=-x4+a1;
  register s12(f4,q,rst,x5);
  assign a2=~f3+1;
  assign f5=x5+a2;
  register s13(f5,q,rst,x6);
  assign a3=~x6+1;
  assign out=w+a3;
  endmodule

 //submodule for counter
module count(clk,rst,in);
  input clk;
  input rst;
  output [7:0]in;
  reg [7:0]in;
  always@(posedge clk)
    if(rst)
      begin
      in=8'b0;
    end
    else
      begin
      in=in+16;
    end
  endmodule

 //sub module for register
  module register(x1,clk,rst,y);
  input [7:0]x1;

  input clk,rst;
  output reg [7:0]y;
  initial
  begin
    y=8'b0;
  end
  always@(posedge clk)
  begin
    if(rst)
      y=8'b0;
    else
        y=x1;
  end
endmodule

//sub module for divition
 module div82(divs,divd,quo);
  input [7:0]divs;
  input [7:0]divd;
  output [7:0]quo;
  wire [15:0]q1;
  wire [7:0]r1,r2,r3,r4,r5,r6,r7,r8;
  assign q1={8'b0,divs};
  div41 d1(q1[14:7],divd[7:0],r1[7:0],quo[7]);
  div41 d2({r1[6:0],divs[6]},divd[7:0],r2[7:0],quo[6]);
  div41 d3({r2[6:0],divs[5]},divd[7:0],r3[7:0],quo[5]);
  div41 d4({r3[6:0],divs[4]},divd[7:0],r4[7:0],quo[4]);
  div41 d5({r4[6:0],divs[3]},divd[7:0],r5[7:0],quo[3]);
  div41 d6({r5[6:0],divs[2]},divd[7:0],r6[7:0],quo[2]);
  div41 d7({r6[6:0],divs[1]},divd[7:0],r7[7:0],quo[1]);
  div41 d8({r7[6:0],divs[0]},divd[7:0],r8[7:0],quo[0]);
endmodule

module div41(divs,divd,rem,quo);
  input [7:0]divs,divd;
  output [7:0]rem;
  output quo;
  reg [7:0]rem;
  reg quo;
  wire [7:0]r,c;
  cas12 c1(divs[0],divd[0],1'b0,r[0],c[0]);
  cas12 c2(divs[1],divd[1],c[0],r[1],c[1]);
  cas12 c3(divs[2],divd[2],c[1],r[2],c[2]);
  cas12 c4(divs[3],divd[3],c[2],r[3],c[3]);
  cas12 c5(divs[4],divd[4],c[3],r[4],c[4]);
  cas12 c6(divs[5],divd[5],c[4],r[5],c[5]);
  cas12 c7(divs[6],divd[6],c[5],r[6],c[6]);
  cas12 c8(divs[7],divd[7],c[6],r[7],c[7]);
  always@(divs or c or r)
  begin
    if(c[7])
      begin
        quo=1'b0;
        rem=divs;
      end
    else
      begin
        quo=1'b1;
        rem=r;
      end
    end
  endmodule
    module cas12(a,b,c,diff,brow);
    input a,b,c;
    output diff,brow;
    assign diff=a^b^c;
    assign brow=((~a)&b)|(b&c)|((~a)&c);
  endmodule


 module div(clk,rst,q);
  input clk,rst;
  output q;
  reg [27:0]sig;
always @(posedge clk)
begin
  if(rst==1)
    sig=28'b0;
  else if (rst==0)
    sig=sig+1;
  end
  assign q=sig[25];
endmodule